(i) Field of the Invention
The present invention relates to a receiver for code division multiple access communication and particularly to a code division multiple access receiver which can improve sensitivity to a received signal amplitude-adjusting signals.
(ii) Description of the Related Art
In recent years, code division multiple access (CDMA) communication system-based digital radio communication is widely used in portable telephones. In the code division multiple communication, a variety of spread codes are used to perform modulation and multiplex the communication, whereby a waste of frequency components can be prevented and the confidentiality of the communication can be maintained advantageously.
In a portable telephone terminal adopting the code division multiple communication system, a code division multiple access receiver for receiving and demodulating a received base band signal is used.
A description will be given to a conventional code division multiple access receiver with reference to FIGS. 4 to 6. FIG. 4 is a block diagram of a conventional code division multiple access receiver. The code division multiple access receiver of FIG. 4 adopts W-CDMA (Wideband Code Division Multiple Access) as a communication system and receives and demodulates a complex-spread and modulated radio signal.
A received base band signal received by an antenna (not shown) is separated into an in-phase component and a quadrature component (indicated as “I phase” and “Q phase” in FIG. 4, respectively; these terms will be used in subsequent drawings), and the in-phase component and the quadrature component are output to a matched filter section (indicated as “MF section” in FIG. 4) 41 and a correlator section 45.
Both components of the received base band signal are subjected to a complex correlation computation with a spread code output from a spread code-generating section 43 in the matched filter section 41, and the results of the correlation computations are output to an electric power-averaging section 42. The spread code output from the spread code-generating section 43 is the same as that used in demodulating the received base band signal.
The electric power-averaging section 42 performs electric power computations based on the correlation computation results output from the matched filter section 41 to determine electric power values, averages the electric power values, and outputs the obtained result of averaging the electric power values to a control section 44.
The control section 44 detects the timing at which the largest electric power value is obtained from the electric power average result and outputs a spread code output timing signal to the spread code-generating section 43 based on the detected timing. The spread code-generating section 43 generates a spread code based on the spread code output timing and outputs the spread code to the matched filter section 41 and the correlator section 45.
Meanwhile, in the correlator section 45, complex correlation computations of both components of the received base band signal and the spread code output from the spread code-generating section 43 are performed, and the result of the correlation computation for each component is output to a storage section 46.
Next, a description will be given to the constitution and operation of the correlator section 45. FIG. 5 is a block-diagram of the correlator section 45.
Of the received base band signal components input into the correlator section 45, the I phase is input into exclusive OR circuits 501 and 510 and the Q phase is input into exclusive OR circuits 502 and 509. Of the spread codes output from the spread code-generating section 43, the one for the I phase is input into the exclusive OR circuits 501 and 509 and the one for the Q phase is input into the exclusive OR circuits 502 and 510.
A computation is performed in each exclusive OR circuit, and the results of the computations in the exclusive OR circuits 501 and 502 are output to an adder 503 to be added. In the correlator section 45 of FIG. 5, either 1 or −1 is input as the spread signal for each component. Since the scale of the circuits increases when the complex correlation computations are performed accurately, the accuracy of the computation results is maintained to some degree by using the exclusive OR circuits in the computations between the received base band signal and the spread code for the purpose of preventing an increase in the scale of the circuits.
The result of the addition in the adder 503 is further subjected to cumulative addition with the result of integrating the output of the adder 503 which is stored in an F/F (Flip Flop) 506 via a selecting section 505, and an updated integration result is input into the F/F 506.
A tip timing clock is input into the F/F 506, and the F/F 506 outputs the stored integration result to the selecting section 505 based on the clock, thereby performing the cumulative addition. The selecting section 505 outputs the integration result output from the F/F 506 to the adder 504 when a symbol timing clock is not input and outputs 0 to the adder 504 when the symbol timing clock is input. According to such a constitution, the correlator 45 can perform the integration of the correlation computation result at each tip timing and discharge the integration result at each symbol timing.
The integration result output from the F/F 506 is also output to a selecting section 507. The selecting section 507 outputs the integration result to an F/F 508 when a symbol timing clock is not input and outputs 0 to the F/F 508 when the symbol timing clock is input.
The F/F 508 stores the largest integration result out of the integration results output from the selecting section 507 and outputs the stored integration result as the complex correlation result of the I phase until 0 is output from the selecting section 507, that is, for a period of one symbol time unit. The complex correlation result of the I phase is calculated according to the constitutions and operations of the above circuits shown in the upper portion of FIG. 5.
The complex correlation result of the Q phase is calculated according to the circuits shown in the lower portion of FIG. 5 in the same manner as in the case of the I phase.
FIG. 6 is a diagram showing the waveforms of the output signals in the correlator section 45. The waveforms of the integration discharge results output from the F/F 506 or 514 are shown in the middle portion of FIG. 6. In reality, the waveforms of integration discharges are expressed as a waveform increasing or decreasing in the form of a staircase per tip time unit. In this case, however, they are expressed as straight lines for brevity.
Meanwhile, the waveform of the complex correlation results output from the F/F 508 or 516 are shown in the lower portion of FIG. 6. It is clear from the waveform of the complex correlation results that the F/F 508 or 516 stores and outputs the largest integration discharge result out of the integration discharge results in the symbol timings (shown in the upper portion of FIG. 6).
As for the size of data processed in the correlator section 45 in FIG. 4, when the received base band signal is 16-bit data and the data rate is 7.5 Ksps (spread factor (SF)=512), for example, the correlator section 45 performs cumulative addition for 512 times per component per symbol and outputs a 25-bit complex correlation result as a result of the cumulative addition.
The complex correlation results of both components which are output from the correlator section 45 are output to the storage section 46. The storage section 46 stores the highest 16 bits of the complex correlation result of each component fixedly for a size of one frame.
The complex correlation results stored in the storage section 46 are further subjected to RAKE synthesis in a RAKE synthesis section 47, and the results of the RAKE synthesis are subjected to soft discrimination, Viterbi decoding and CRC checking in an error-correcting section 48 to correct errors and output the resulting data as demodulated data.
In the code division multiple access receiver of FIG. 4, the timing at which the electric power value of the correlation computation results of the received signal and the spread code is maximum, that is, synchronous timing, is detected in the matched filter section 41 and the electric power-averaging section 42 and reflected on the spread code output timing of the spread code-generating section 43, and modulation is performed through the correlation computations of the received signal and the spread code in the correlator section 45 and the RAKE synthesis.
However, the above conventional code division multiple access receiver has the problem that the accuracy of the demodulation process cannot be maintained at a good level.
When the level of a 16-bit received signal to reach the receiver is degraded to ¼ due to an environmental change in transmission lines, the highest 2 bits out of the highest 16 bits of the complex correlation result of each component which are stored in the storage section 46 become invalid. When the level of the received signal is degraded to ⅛, 1/16 or 1/32 for the same reason, the highest 3 bits, 4 bits or 5 bits of the complex correlation result become invalid, respectively. Thus, the conventional code division multiple access receiver has the problem that such degradation in the level of the received signal lowers the accuracy of the demodulation process in the RAKE synthesis section 47 and the error-correcting section 48.
Further, when the symbol rate of the received signal is doubled, the spread factor is reduced to half, so that the number of chips per symbol is reduced to half and the highest 1 bit of the integration result becomes invalid. Further, when degradation in the level of the received signal occurs, the number of invalid bits in the complex correlation result is increased, so that the accuracy of the demodulation process is further lowered.
As a method for decreasing the number of such invalid bits in the correlation result, a method can be mentioned in which all the 25 bits of the complex correlation result are stored in the storage section 46 and the 25-bit data are subjected to the demodulation process in the RAKE synthesis section 47 and the error-correcting section 48 to secure a valid data portion. However, when this method is used, the scales of circuits for storing the correlation results and for performing computations and the amount of computation are increased, so that the consumption of electric power increases.